The present invention relates to electrical circuits and, more particularly, to emitter-coupled logic circuits applicable to gate array designs.
Gate arrays are semiconductor devices with standard doping layers and customizable metallization layers. Gate arrays allow a design effort to obtain application specific integrated circuits while avoiding the long lead times involved in designing a circuit from scratch. Since they are neither off-the-shelf items, nor entirely customized circuits, gate arrays are considered semi-custom devices. Gate arrays can be fabricated according to a variety of process technologies such as complementary metal-on-oxide (CMOS) and bipolar emitter-coupled logic (ECL) technologies.
When high speeds are required, ECL is often the technology of choice. Rather than switching current on and off as in conventional CMOS circuits, ECL circuits redirect a constant magnitude network current through alternate paths. A typical ECL circuit includes a voltage source, a current network, and a gating system. The voltage source is generally referred to by separate high (V.sub.cc) and low (V.sub.ee) voltage components. The voltage source applies a potential difference across the network so as to generate a current through one, or sometimes more, of the paths that constitute the network. The gating system determines the path or paths through which the network current flows at any given time.
An elementary gate includes a "switching" transistor and a "reference" transistor. The transistors are characterized by the voltages applied to their bases. The voltage applied to the base of a "reference" transistor is a constant reference voltage (V.sub.bb), usually between V.sub.cc and V.sub.ee.The voltage applied to the base of a "switching" transistor is usually discretely variable between a voltage above V.sub.bb and a voltage below V.sub.bb.
The operation of the elementary gate is straightforward. When the voltage at the base of the switching transistor is below the reference voltage V.sub.bb, current flows from the high voltage source, through the reference transistor via its respective load resistor, and eventually to the low voltage source. Alternatively, when the voltage applied to the base of the switching transistor is higher than the reference voltage V.sub.bb, current flows through the switching transistor. Thus, the path of the current through the gate is determined by controlling the voltage at the base of the switching transistor.
Because a typical ECL circuit may have many current networks and many gates, the reference voltage source typically is coupled to the circuit components through a bus. At the lower currents employed in conventional circuits, this proves t o be a reliable method for distributing the reference voltage V.sub.bb throughout the system because the resistivity of the bus is ordinarily negligible. However, present-day ECL circuits must accommodate currents on the order of two or more amperes. The present inventors have discovered that because of such high currents and the temperature variations they cause, the reference voltage often drops significantly as it propagates through the bus. Consequently, circuit components disposed on the end of the bus and away from the reference voltage source receive a voltage which differs significantly from the intended reference voltage, so the actual current paths within the ECL circuit vary from the expected current path for a given reference potential. Although one solution to the problem is limiting the length of the reference voltage bus and providing multiple sources of the reference voltage, the cost of the multiple reference voltage sources and the constraints imposed by short bus lengths would be prohibitive given the competitive condition of the gate array industry.